Modern electronic devices generally employ electrical signals at varying voltages, one of which indicates a logic ‘1,’ while another indicates a logic ‘0.’ The particular voltages representing logic ‘1’ and ‘0’ defines a logic family. The logic family can be implemented in a variety of logic or design styles. One popular logic style is Complementary Metal-Oxide Semiconductor (CMOS).
CMOS is popular in the design of digital integrated circuits in part due to certain technical advantages. For example, CMOS systems generally exhibit very low static-power dissipation, high packing density, and wide noise margins. However, common CMOS systems often suffer from large dynamic power dissipation at high-frequencies. CMOS systems are also highly susceptible to environmental noise and are limited in their maximum operating frequency. The CMOS maximum frequency limitation arises for a variety of reasons, such as device mismatch and voltage rail noise, for example. This problem is exacerbated in some high speed analog circuit designs. For example, in an analog system running at 8 GHz, it is not unreasonable to have tolerances of <5 ps of jitter.
Current Mode Logic (CML) is a differential digital logic family that overcomes some of the shortcomings of standard CMOS systems. Generally, CML systems transmit data at speeds between 312.5 Mbit/s and 3.125 Gbit/s over standard printed circuit boards, using point-to-point, unidirectional transmission. Generally, a CML circuit operates at a lower signal voltage, higher operating frequency, and lower supply voltage than the corresponding CMOS circuit.
Specifically, CML circuits employ differential signaling and rely on fully differential amplifiers. Differential signaling eliminates common mode noise, which also reduces total noise. Additionally, a constant DC current flows through each differential amplifier, steered from one leg of the amplifier to the other, to provide the signaling scheme based on the CML logic family used in the circuit. The supply noise and droop associated with the constant current is significantly lower than that found in common CMOS systems.
Typical CML circuits employ one or both of two characteristic logic families, which differ from static CMOS logic families. For example, in static CMOS, the typical logic family assigns logic ‘0’ to ground and logic ‘1’ to the supply voltage, such as 1.2V, for example.
CML circuits instead employ two distinct logic families called “nCML” and “pCML,” both of which use differential signaling. The nCML logic family assigns logic ‘1’ to the supply voltage, for example, 1.2 volts. nCML standards define logic ‘0’ as an offset from logic ‘1.’ For example, in one common system nCML logic ‘0’ is approximately 400 mV less than the supply voltage. Thus, where the supply voltage is 1.2V, the nCML logic ‘0’ is 800 mV. The pCML logic family assigns logic ‘0’ to ground, and defines logic ‘1’ as an offset from ground. For example, in one common system pCML logic ‘1’ is 400 mV.
Each CML family offers particular advantages. For example, the nCML family offers greater gain, and the pCML family offers better noise immunity. In both cases, however, the voltage swing from logic high to logic low is less than the difference between the supply voltage and ground. As such, the relatively smaller differential voltage steers current in the differential amplifiers such that the amplifiers remain in saturation mode.
As nCML and pCML have particular advantages, there are times when a designer desires to mix both logic families together in a particular architecture. However, nCML and pCML circuits have very different design requirements. As such, architectures employing both logic families require differential level translators to convert a CML signal from one logic family to another.
Conventional approaches to converting between CML logic families suffer from significant drawbacks. For example, known CML converters are frequently complex and take up a large circuit area. Additionally, typical CML converters convert from CML to an intermediate format, such as CMOS for example, thereby introducing increased power dissipation and delay. Moreover, the conversion process frequently strips the differential signal into two distinct signals, which must be converted back to a differential signal, which can introduce error.